Design And Construction Of A False Triggering Eliminator For Timer 555

Overview

ABSTRACT

Normally, false triggering of timer IC 555 takes place during power on, resulting in unwanted output, which starts the timer’s time cycle. The circuit becomes inefficient especially when the load has to be energised only when desired. This work is on a simple false triggering eliminator circuit for timer 555. The circuit is wired in monostable mode and grounded via N/O contact of RL(b) as well as switch S2. When power switch S1 is switched on, the circuit will not be grounded until switch S2 is momentarily pressed.

TABLE OF CONTENTS

TITLE PAGE

APPROVAL PAGE

DEDICATION

ACKNOWLEDGEMENT

ABSTRACT

TABLE OF CONTENT

CHAPTER ONE

1.0      INTRODUCTION

1.1      BACKGROUND OF THE PROJECT
1.2      AIM OF THE PROJECT
1.3      OBJECTIVE OF THE PROJECT
1.4      SIGNIFICANCE OF THE PROJECT
1.5      PURPOSE OF THE PROJECT
1.6      APPLICATION OF THE PROJECT
1.7      ADVANTAGES OF THE PROJECT
1.8      PROBLEM/LIMITATION OF THE PROJECT
1.9      PROJECT ORGANISATION

CHAPTER TWO

2.0     LITERATURE REVIEW

2.1      REVIEW OF RELATED STUDIES

2.2      REVIEW OF RELATED TERMS

CHAPTER THREE

3.0     CONSTRUCTION METHODOLOGY

3.1      SYSTEM CIRCUIT DIAGRAM

3.2     SYSTEM OPERATION

3.3      CIRCUIT DESCRIPTION

3.4      SYSTEM CIRCUIT DIAGRAM

3.5      CIRCUIT OPERATION

3.6      IMPORTANCE AND FUNCTION OF THE MAJOR COMPONENTS USED IN THIS CIRCUIT

3.7      POWER SUPPLY UNIT

CHAPTER FOUR

RESULT ANALYSIS

4.0      CONSTRUCTION PROCEDURE AND TESTING

4.1      CASING AND PACKAGING

4.2      ASSEMBLING OF SECTIONS

4.3      TESTING

4.4.1 PRE-IMPLEMENTATION TESTING

4.4.2  POST-IMPLEMENTATION TESTING

4.5      RESULT

4.6      COST ANALYSIS

4.7      PROBLEM ENCOUNTERED

CHAPTER FIVE

5.1      CONCLUSION

5.2      RECOMMENDATION

5.3      REFERENCES

False Triggering Eliminator Circuit

The circuit is wired in monostable mode and grounded via N/O contact of RL(b) as well as switch S2. When power switch S1 is switched on, the circuit will not be grounded until switch S2 is momentarily pressed. To provide the triggering pulse to the timer at pin 2, press switch S2 momentarily.

False Triggering Eliminator Circuit for Timer 555

To activate the relay for operating the load, switch on the power to the circuit by pressing switch S1 and then S2 momentarily. The resulting output at pin 3 goes high and energises relay RL to operate the load. Now after momentarily pressing S2, the circuit remains on as GND gets connected to N/O contact of RL(b). At the same time, pin 2 is disconnected from N/C contact of RL(b), which prevents further triggering.

The time period of relay energisation (approximately 3 minutes) can be easily changed by changing the values of resistor R1 and capacitor C1 according to the requirement to operate the load. At the end of the cycle, the relay gets de-energised and the circuit becomes ungrounded again.

 

Research Guidelines

The Title Page should be the first section of your project “Design And Construction Of A False Triggering Eliminator For Timer 555”, providing essential details like the project title, your name, your supervisor’s name, the institution, and the submission date. After that, the Abstract offers a brief summary of your project, touching on its purpose, methods, results, and conclusions in 150-300 words. The Acknowledgments section is where you can thank those who supported your research, such as your supervisor, peers, or organizations that provided resources.

Next, the Table of Contents organizes the Design And Construction Of A False Triggering Eliminator For Timer 555 by listing its chapters and sections, along with page numbers for easy reference. The List of Figures and List of Tables help guide readers to specific visual elements like graphs, charts, or tables included in the document. There should also be an Abbreviations and Glossary section to explain any specialized terms or acronyms, making the content clearer to readers unfamiliar with the technical language.

The main body of the Design And Construction Of A False Triggering Eliminator For Timer 555 should start with the Introduction, which provides background information, outlines the research problem, states your objectives, and gives a brief overview of your research methods. Following that, the Literature Review offers an in-depth look at previous research relevant to your project, identifying gaps your study aims to address. The Methodology section then explains the research design, tools, and data collection methods you used to conduct the project and analyze the data.

In the Results and Discussion section, you present your findings and discuss them in relation to the Design And Construction Of A False Triggering Eliminator For Timer 555 research questions or objectives, often using tables or charts to help explain the data. The Conclusion summarizes the key results, discusses their implications, and suggests possible directions for future research. You may also include recommendations based on your findings, offering practical advice for improvements or applications. Finally, the Design And Construction Of A False Triggering Eliminator For Timer 555 project should include a References or Bibliography section to list all the sources you cited, as well as Appendices for any additional material. A Statement of Originality is often included to confirm the authenticity of your work